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stv9427 STV9428-STV9429 high speed multisynch on-screen display for monitor june 1998 . cmos single chip osd for monitor . built in 1 kbyte ram holding : - character codes - user definable characters . 207 alphanumeric characters or graphic symbols in internal rom . 12 x 18 character dot matrix . programmable accentuated charac- ter set . character blinking . ram definable color look up table . up to 16 user definable characters . up to 80mhz pixel clock . internal horizontal pll (15 to 120khz) . programmable vertical height of character with a slice interpolator to meet multi-synch requirements . programmable vertical and hori- zontal positioning . flexible screen description . 22 control codes for powerfull serial attributes . 2-wires asynchronous serial mcu interface (i 2 c protocol) . 8 x 8 bits pwm dac outputs . single positive 5v supply dip16 (plastic package) order code : stv9427 description the stv9427/28/29 is an on screen display for monitor. it is built as a slave peripheral con- nected to a host mcu via a serial i 2 c bus. it includes a display memory, controls all the display attributes and generates pixels from the data read in its on chip memory. the line pll and a special slice interpolator allow to have a display aspect which does not depend on the line and frame frequencies. i 2 c interface allows mcu to make transparent internal access to prepare the next pages during the display of the current page. tog- gle from one page to another by programming only one register. dip24 (plastic package) order code : stv9429 8 x 8 bits pwm dac are available to provide dc voltage control to other peripherals. the stv9427/28/29 provides the user an easy to use and cost effective solution to display alphanu- meric or graphic information on monitor screen. dip20 (plastic package) order code : stv9428 1/20
pin description symbol pin number i/o description dip24 dip20 dip16 pwm6 1 - - o dac0 output pwm1 2 1 - o dac1 output v dd1 3 2 1 s +5v logic supply tst 4 3 2 i reserved (not to be connected) xto 5 4 3 o crystal output xti 6 5 4 i crystal or clock input reset 7 6 5 i reset input (active low) vsync 8 7 6 i vertical sync input hsync 9 8 7 i horizontal sync input gnd 10 9 8 s logic ground pwm2 11 10 - o dac2 output pwm5 12 - - o dac3 output pwm4 13 - - o dac4 output pwm3 14 11 - o dac5 output scl 15 12 9 i serial clock sda 16 13 10 i/o serial input/output data gnd 17 14 11 s ground fblk 18 15 12 o fast blanking output r 19 16 13 o red output g 20 17 14 o green output b 21 18 15 o blue output v dd2 22 19 16 s +5v outputs supply pwm0 23 20 - o dac6 output pwm7 24 - - o dac7 output 9427-01.tbl 9427-01.eps / 9428-01.eps / 9429-01.eps pin connections 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd1 tst xto vsync hsync xti v dd2 b g r fblk reset sda scl gnd gnd dip16 (stv9427) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 24 23 22 21 11 12 pwm7 pwm0 pwm3 pwm4 pwm5 pwm2 pwm1 pwm6 sda scl fblk b g r reset tst xto vsync hsync xti gnd gnd v dd2 v dd1 dip24 (stv9429) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 pwm0 pwm3 pwm2 pwm1 sda scl fblk v dd1 b g r reset tst xto vsync hsync v dd2 xti gnd gnd 14 13 12 11 dip20 (stv9428) stv9427 - stv9428 - stv9429 2/20
12 6 7 2 3 4 9 10 5 11 13 14 15 16 hsync vsync reset rgbfblk gnd scl sda xti xto tst v dd2 address/data horizontal digital pll 4k rom display controller i c bus interface 2 stv9427 1 v dd1 1k ram 8 gnd 9427-02.eps block diagrams stv9427 pwm5 pwm2 pwm1 pwm6 pwm7 pwm0 pwm3 pwm4 hsync vsync reset rgbfblk gnd scl sda xti xto tst v dd1 address/data horizontal digital pll 4k rom display controller 9 8 7 19 20 21 18 17 15 16 stv9429 6 5 4 10 3 pwm v dd2 22 1k ram gnd 12 11 2 1 24 23 14 13 i 2 c bus interface 9429-02.eps stv9429 hsync vsync reset rgbfblk gnd scl sda xti xto tst v dd1 address/data horizontal digital pll 4k rom display controller i 2 c bus interface 8 7 6 16 17 18 15 14 12 13 stv9428 5 4 3 9 2 pwm v dd2 19 1k ram gnd pwm0 pwm3 pwm2 11 10 1 pwm1 20 9428-02.eps stv9428 stv9427 - stv9428 - stv9429 3/20
absolute maximum ratings symbol parameter value unit v dd supply voltage -0.3, +7.0 v v in input voltage -0.3, +7.0 v t oper operating temperature 0, +70 c t stg storage temperature -40, +125 c 9427-02.tbl electrical characteristics (v dd1 = v dd2 = 5v, v ss = 0v, t a = 0 to 70c, f xtal = 8 to 15mhz, test = 0 v, unless otherwise specified) symbol parameter min. typ. max. unit supply v dd supply voltage 4.75 5 5.25 v i dd supply current - 65 90 ma inputs scl, sda, reset, vsync and hsync v il input low voltage 0.8 v v ih input high voltage 2.4 v i il input leakage current -10 +10 m a outputs sda open drain and pwmi (i = 0 to 7) v ol output low voltage (i ol = 1.6ma) 0 0.4 v v oh output high voltage (i oh = -0.1ma) 0.9v dd v dd v r, g, b, fblk v ol output low voltage (i ol = 1.6ma) 0 0.4 v v oh output high voltage (i oh = -0.1ma) 0.9v dd v dd v 9427-03.tbl 5 2.5 0 10 -5 10 -4 10 -3 10 -2 10 -1 i (a) (v) , v ol oh v v ol oh v 9427-17.eps figure 1 : r, g, b, fblk typical outputs static characteristics stv9427 - stv9428 - stv9429 4/20
timings symbol parameter min. typ. max. unit oscilator input : xti (see figure 2) t wh clock high level 20 ns t wl clock low level 20 ns f xtal clock frequency 6 15 mhz f pxl pixel frequency 30 80 mhz reset t res reset low level pulse 4 m s r, g, b, fblk (c load = 30pf) t r rise time (see note 1) 5 ns t f fall time (see note 1) 5 ns t skew skew between r, g, b, fblk 5 ns i 2 c interface : sda and scl (see figure 3) f scl scl clock frequency (horizontal frequency = 32khz) 288 khz t buf time the bus must be free between 2 access 500 ns t hds hold time for start condition 500 ns t sup set up time for stop condition 500 ns t low clock low level 400 ns t high clock high level 400 ns t hdat hold time data 0 ns t sudat set up time data 500 ns t f sda fall time 20 ns t r scl and sda rise time depend on the pull-up resistor and on the load capacitance note 1 : these parameters are not tested on each unit. they are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization. 9427-04.tbl xti t wh t wl 9427-03.eps figure 2 sda scl stop start data stop t buf t sup t hdat t sudat t hds t high t low 9427-04.eps figure 3 stv9427 - stv9428 - stv9429 5/20
functional description the stv9427/28/29 display processor operation is controlled by a host mcu via the i 2 c interface. it is fully programmable through internal read/write reg- isters and performs all the display functions by generating pixels from data stored in its internal memory. after the page downloading from the mcu, the stv9427/28/29 refreshes screen by its built in processor, without any mcu control (access). in addition, the host mcu has a direct access to the on chip 1kbytes ram during the display of the current page to make any update of its contents. with the stv9427/28/29, a page displayed on the screen is made of several strips which can be of 2 types : spacing or character and which are de- scribed by a table of descriptors and character codes in ram. several pages can be downloaded at the same time in the ram and the choice of the current display page is made by programming the display control register. i - serial interface the 2-wires serial interface is an i 2 c interface. to be connected to the i 2 c bus, a device must own its slave address ; the slave address of the stv9427/28/29 is ba (in hexadecimal). a6 a5 a4 a3 a2 a1 a0 r/w 1011101 i.1 - data transfer in write mode the host mcu can write data into the stv9427/28/29 registers or ram. to write data into the stv9427/28/29, after a start, the mcu must send (figure 4) : - first, the i 2 c address slave byte with a low level for the r/w bit, - the two bytes of the internal address where the mcu wants to write data(s), - the successive bytes of data(s). all bytes are sent msb bit first and the write data transfer is closed by a stop. each byte is synchronously transfered at each hsync period. i.2 - data transfer in read mode the host mcu can read data from the stv9427/28/29 registers, ram or rom. to read data from the stv9427/28/29 (figure 5), the mcu must send 2 different i 2 c sequences. the first one is made of i 2 c slave address byte with r/w bit at low level and the 2 internal address bytes. the second one is made of i 2 c slave address byte with r/w bit at high level and all the successive data bytes read at successive addresses starting from the initial address given by the first sequence. each byte is synchronously transfered at each hsync period. the first data byte, in read mode, is available one hsync period after the acknow- ledge of the address byte. scl sda r/w a7 a6 a5 a4 a3 a2 a1 a0 - - a13 a12 a11 a10 a9 a8 i 2 c slave address ack lsb address ack msb address ack start d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ack ack data byte 1 data byte 2 ack data byte n stop scl sda 9427-05.eps figure 4 : mcu i 2 c write operation scl sda r/w a7 a6 a5 a4 a3 a2 a1 a0 i 2 c slave address ack lsb address ack msb address ack start -- a13 a12 a10 a10 a9 a8 stop scl sda r/w d7 d6 d5 d4 d3 d2 d1 d0 i 2 c slave address ack ack data byte n ack start d7 d6 d5 d4 d3 d2 d1 d0 stop data byte 1 * 9427-06.eps note : the first data bit out (d7) is valid after one scanline period. figure 5 : mcu i 2 c read operation stv9427 - stv9428 - stv9429 6/20
functional description (continued) i.3 - addressing space i.3.1 - general mapping stv9427/28/29 registers, ram and rom are mapped in a 16kbytes addressing space. the mapping is the following : 0000 03ff 1024 bytes ram descriptors character codes and user definable characters 0400 empty space 07ff 0800 character generator rom 3fbf 3fc0 empty space 3fd0 3fcf internal registers 3fd0 i.3.2 - i 2 c registers mapping 3fcf 3fd0 pwm0 pwm registers pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 3fd7 pwm7 3fd8 reserved 3fdf 3fe0 color 0 color look-up table (clut) color 1 color 2 color 3 color 4 color 5 color 6 3fe7 color 7 3fe8 color 8 color 9 color 10 color 11 color 12 color 13 color 14 3fef color 15 3ff0 line duration top margin horizontal delay character height display control control registers locking time constant capture time constant initial pixel period 3ff8 frequency multiplier 3ff9 reserved 3fff i.4 - register set i.4.1 - pwm registers the eight registers described below are only avail- able with the stv9429 : pulse width modulator 0 (stv9429) 3fd0 v07 v06 v05 v04 v03 v02 v01 v00 v0[7:0] : digital value of the 1 st pwm d to a converter. pulse width modulator 1 (stv9429) 3fd1 v17 v16 v15 v14 v13 v12 v11 v10 v1[7:0] : digital value of the 2 nd pwm dac. pulse width modulator 2 (stv9429) 3fd2 v27 v26 v25 v24 v23 v22 v21 v20 v2[7:0] : digital value of the 3 rd pwm dac. pulse width modulator 3 (stv9429) 3fd3 v37 v36 v35 v34 v33 v32 v31 v30 v3[7:0] : digital value of the 4 th pwm dac. pulse width modulator 4 (stv9429) 3fd4 v47 v46 v45 v44 v43 v42 v41 v40 v4[7:0] : digital value of the 5 th pwm dac. pulse width modulator 5 (stv9429) 3fd5 v57 v56 v55 v54 v53 v52 v51 v50 v5[7:0] : digital value of the 6 th pwm dac. pulse width modulator 6 (stv9429) 3fd6 v67 v66 v65 v64 v63 v62 v61 v60 v6[7:0] : digital value of the 7 th pwm dac. pulse width modulator 7 (stv9429) 3fd7 v77 v76 v75 v74 v73 v72 v71 v70 v7[7:0] : digital value of the 8 th pwm dac. note : power on reset default value of pmw register is 00h stv9427 - stv9428 - stv9429 7/20
i.4.2 - look-up table registers color look-up table [clut] is read/write ram table. mapping address is described in chapter i.3.2. the clut is splitted in 2 blocks of 8 bytes. each byte contains foreground and background informa- tions as described below : sha br bg bb fl fr fg fb sha : shadowing fl : flashing foreground br, bg, bb : background color fr, fg, fb : foreground color if sha = 1 and br = bg = bb = 0, the background of the character is transparent. each block may store a different set of colors. one block of colors may be used for the normal items of the menu while the second block, with brighter colors, may be used for selected items of the menu. the block selection is done by programming bit clu3 of clu[3:0] of the character descriptor (see table 1). it remains selected all the row long. bit clu2, clu1 and clu0 of clu[3:0] of the character descriptor select the active color at the beginning of the row. the active color can be changed along the row, using 8 control codes col0 to col7. each control code (col0 to col7) active a dedicated color byte in the clut as described in table 2. table 1 : clut block selection clu3 clu[2:0] code name ram @(hex) reset value (hex) 0 0 col 0 @3fe0 07 1 col 1 @3fe1 16 2 col 2 @3fe2 25 3 col 3 @3fe3 34 4 col 4 @3fe4 43 5 col 5 @3fe5 52 6 col 6 @3fe6 61 7 col 7 @3fe7 70 1 0 col 0 @3fe8 70 1 col 1 @3fe9 61 2 col 2 @3fea 52 3 col 3 @3feb 43 4 col 4 @3fec 34 5 col 5 @3fed 25 6 col 6 @3fee 16 7 col 7 @3fef 07 table 2 : clut color selection code name code nbr (h) color look-up table in ram col1 10 @ 3fe0 : color 0 col2 11 @ 3fe1 : color 1 col6 16 @ 3fe6 : color 6 col7 17 @ 3fe7 : color 7 col0 10 @ 3fe8 : color 8 col1 11 @ 3fe9 : color 9 col6 16 @ 3fee : color 14 col7 17 @ 3fef : color 15 i.4.3 - control registers line duration (reset value : 20h) 3ff0 vsp hsp ld6 ld5 ld4 ld3 ld2 ld1 vsp : v-sync active edge selection = 0, falling egde, = 1, rising edge. hsp : h-sync active edge selection = 0, falling egde, = 1, rising edge. ld[6:1] : line duration ld0 = 0 ld1 = 2 periods of character one character period is 12 pixels long. top margin (reset value : 60h) 3ff1 m8 m7 m6 m5 m4 m3 m2 m1 m[8:1] : top margin height from the vsync reference edge. m0 = 0 m1 = 2 scan lines note : the top margin is displayed before the first strip of descriptor list. it can be black if fbk of display control register is set or transparent if fbk is clear. horizontal delay (reset value : 20h) 3ff2 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 dd[7:0] : horizontal display delay from the hsync reference edge to the 1 st pixel position of the character strips. unit = 6 pixel periods. minimum value is 08h. first pixel position = [dd[7:0] - 6] x 6 + 54. with dd[7:0] = 1,3,5 then the delay is 60 pixel. functional description (continued) stv9427 - stv9428 - stv9429 8/20
characters height (reset value : 24h) 3ff3 - - ch5 ch4 ch3 ch2 ch1 ch0 ch[5:0] : height of the character strips in scan lines. for each scan line, the number of the slice which is displayed is given by : slice-number = round ? ? scan - line - number x 18 ch[5:0] ? ? . scan-line-number = number of the current scan line of the strip. display control (reset value : 00h) 3ff4 osd fbk fl1 fl0 p9 p8 p7 p6 osd : on/off (if 0, r, g, b and fblk outputs are 0). fbk : fast blanking control : = 1, forces fblk pin at "1" outside and inside the osd area. this leads to blank video rgb and to only display osd rgb. = 0, fblk pin is driven according character code for normal display of osd data. fl[1:0] : flashing mode : - 00 : no flashing. the character attribute is ignored, - 01 : flashing at f f (50% duty cycle), - 10 : flashing at 2 f f , - 11 : flashing at 4 f f . note : f f is 128 time vertical frequency. p[9:6] : address of the 1 st descriptor of the current displayed pages. p[13:10] and p[5:0] = 0 ; up to 16 different pages can be stored in the ram. locking condition time constant (reset value : 01h) 3ff5 fr as2 as1 as0 luk bs2 bs1 bs0 fr : free running ; if = 1 pll is disabled and the pixel frequency keeps its last value. as[2:0] : phase constant during locking conditions. bs[2:0] : frequency constant during locking conditions. luk : lock unlock status bit 0 = unlocked pll 1 = locked pll capture process time constant (reset value : 24h) 3ff6 len af2 af1 af0 - bf2 bf1 bf0 len : lock enable 0 = r,g,b, fblk are always enabled, 1 = r,g,b, fblk are enabled only when pll is locked. af[2:0] : phase constant during the capture process. bf[2:0] : frequency constant during the capture process. initial pixel period (reset value : 28h) 3ff7 pp7 pp6 pp5 pp4 pp3 pp2 pp1 pp0 pp[7:0] : v alue to initialize the pixel period of the pll. frequency multiplier (reset value : 0ah) 3ff8----fm3fm2fm1fm0 fm[3:0] : frequency multiplier of the crystal frequency to reach the high frequency used by the pll to derive the pixel frequency. note : for high pixel frequency (over 70mhz), write at address 3fff, data f0h. ii - descriptors spacing msb 0 l/ c------ lsb sl7 sl6 sl5 sl4 sl3 sl2 sl1 sl0 l/ c : line or character spacing : = 0, spacing descriptor defined as character height (sl[7:0] = 1 to 255 character). = 1, spacing descriptor defined as scan line height (sl[7:0] = 1 to 255 scan lines). sl[7:0] : number of selected height (character or scan lines according l/ c). character msb 1 de clu3 clu2 clu1 clu0 c9 c8 lsbc7c6c5c4c3c2c1uen de : display enable : = 0, r = g = b = 0 and fblk = fbk bit of display control register on the whole strip, = 1, display of the characters. clu[3:0] : active color selection at the begining of the strip. c[9:1] : address of the first character code of the strip. uen : udc enable 0 : codes 240 to 254 (foh to feh) are read in rom, 1 : codes 240 to 255 (foh to ffh) are read in ram (udc). functional description (continued) stv9427 - stv9428 - stv9429 9/20
iii - code format the codes of stv9427/28/29 are all single byte codes. there are basically 3 kinds of code : - the control codes from 0 to 27 (00h to 1bh) and from 224 to 239 (e0h to efh). - the rom character codes from 32 to 223 (20h to dfh) and from 240 to 255 (f0h to ffh). - the user definables characters codes from 240 to 254 (f0h to ffh). each row must begin with a displayable character code followed by a nop or any control code. for code definition see table 4. iii.1 - control codes control codes must be followed by a displayable code (from 32 to 223), except for rtn & eol. they must not be used twice consecutively without a displayable code between them. the control code call is preceded by an address byte. the control codes are not displayed except if men- tioned. code 0 (00h) : nop : no operation and no display is performed, can be used to spare a location in ram for an active control code. codes 1 to 7 (01h to 07h) : symetries : tshs(01) top side horizontal symetry code displays the top half side of the following displayable code symetricaly to the bottom side. bshs(02) bottom side horizontal symetry code displays the bottom half side of the following displayable code symetricaly to the top side. hflip(03) horizontal flip code flips horizontaly the following displayable code. lsvs(04) left side vertical symetry code displays the left half side of the following displayable code symetricaly to the right side. rsvs(05) right side vertical symetry code displays the right half side of the following displayable code symetricaly to the left side. vflip(06) vertical flip code flips verticaly the following displayable code. hvflip(07) horizontal & vertical flip code flips horizontaly and verticaly the following displayable code. codes 8 (08h) (at odd @) : rtn : return to the call + 1 code location (see note). code 09 to 14 (09h to 0eh) : reserved code 15 (0fh) : eol, end of line terminates the display of the current row. codes 16 to 23 (10h to 17h) : col0 to col7 codes select 1 byte among 8 within the clut in ram. the block selection is fixed by clu3 bit of the active character descriptor (see table 1 and table 2). codes 24 to 27 (18h to 19h) : call, these control codes switch the display of the next character to the code address given by the next byte as following : call code (odd @) msb 0001100a9 address byte (even @) lsb a8 a7 a6 a5 a4 a3 a2 a1 a[9:1] : address of the next code to be used (a0 = 0 only even addresses). notes : call and rtn code must be used twin. they cannot be nested. call and rtn codes are displayed as a space character. call and rtn codes must be placed at odd addresses. they may be preceed by a nop in order to place them at the right position. codes 28 to 31 (1ch to 1fh) : reserved code 224 to 239 (e0h to efh) : accent shapes from 224 to 239 (e0h to efh) are used combined with all other character codes 32 to 223 (10h to dfh) and placed before the target character. the first set of accents, 224 to 231 (e0h to e7h) must be used with lower case letters. the 5 upper slices of the target character are replaced by the accent shape. the second set of accents, 232 to 239 (e8h to efh) must be used with the upper case letters (capital letters). the 3 upper slices of the target character are replaced by the accent shape. accent code must always be followed by a displayable character or a space. iii.2 - rom character codes codes 32 to 223 (20h to dfh) and codes 240 to 254 (f0h to feh) : rom character shapes are described as 12x18 pixel matrix as shown in table 5. it comprises 60 logos dedicated for monitor application (horizontal position, keystone, ...), 25 characters for horizontal bar-graph and additional shapes. functional description (continued) stv9427 - stv9428 - stv9429 10/20
table 4 code n msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lsb hex 0 1 2 3456 7 8 9 a b c d e f 0 0 nop col0 space 0 @ p p ? cont1 hlin1 box0 bar5 bar21 dn r 1 1 tshs col1 ! 1 a q a q ? cont2 hlin2 box1 bar6 bar22 up g 2 2 bshs col2 " 2 b r b r ? bright kystn box2 bar7 10o ^ dn b 3 3 hflip col3 # 3 c s c s ? color kybal1 box3 bar8 1o0 x dn 1 4 4 lsvs col4 $ 4 d t d t ? spkr kybal2 box4 bar9 indxrgt ~ dn 2 5 5 rsvs col5 % 5 e u e u ? mute pincus box5 bar10 indxup up clock0 6 6 vflip col6 & 6 f v f v ? dgaus pinbal box6 bar11 rtn dot dn clock1 7 7 hvflip col7 7 g w g w ? balance tilt1 box7 bar12 hbar0 .. dn clock2 8 8 rtn call ( 8 h x h x 1/2 vfcus tilt2 box8 bar13 hbar1 up a 99-call 9 i y i y 1/4 hfcus cornr0 box9 bar14 vbar0 up e 10 a - - * : j z j z 3/4 vsz cornr1 box10 bar15 vbar1 ^ up t 11 b - - + ; k [ k { ? vpos cornr2 bar0 bar16 treble x up s 12 c - - , < l ? l | o vlin cornr3 bar1 bar17 bass ~ up z 13 d - - - = m ? m << fh hsz cornr4 bar2 bar18 mic up l 14 e - - . ? n n arr if fv hpos1 kh bar3 bar19 upidx0 dot up d 15 f eol - / ? o _ o arr up hz hpos2 hz bar4 bar20 upidx1 .. up 9427-09.tbl functional description (continued) stv9427 - stv9428 - stv9429 11/20
udc location character organization slicer organization xxxx11109 8765432 0 1 msb lsb 00 00 63 code 240/f0h 127 code 241/f1h 191 code 242/f2h code 243/f3h code 244/f4h code 245/f5h code 246/f6h code 247/f7h code 248/f8h code 249/f9h code 250/fah code 251/fbh code 252/fch code 253/fdh code 254/feh 960 1023 code 255/ffh 64 128 255 192 256 319 320 383 384 447 448 511 512 575 576 639 640 703 704 767 768 831 832 896 895 959 40 80 3c0 3f 7f bf c0 ff 100 140 180 1c0 200 240 280 2c0 300 340 380 01 00 03 02 05 04 07 06 09 08 0b 11 0a 10 0d 13 0c 12 0f 15 0e 14 11 17 10 16 19 18 21 20 23 22 25 24 27 26 29 28 31 30 21 33 20 32 35 34 37 36 39 38 41 40 43 42 45 44 47 46 31 49 30 48 51 50 53 52 55 54 57 56 59 58 61 60 3f 63 3e 62 slice 0 slice 1 slice 2 slice 3 slice 4 slice 5 slice 6 slice 7 slice 8 slice 9 slice 10 slice 11 slice 12 slice 13 slice 14 slice 15 slice 16 slice 17 unused unused unused unused unused unused unused unused unused unused unused unused unused unused code number ram location hex dec slice offset hex dec hex dec 9427-18.eps figure 6 : user definable character codes functional description (continued) iii.3 - user definable character codes (udc) codes 240 to 254 (f0h to feh) refer to character shape loaded in ram. the stv9427/28/29 allows the user to dynamically define character(s) for his own needs (for a special logo for example). like the rom characters, a udc is made of a 12 pixels x 18 slices dot matrix. in a udc, each pixel is defined with a bit, 1 refers to foreground, and 0 to background color. each slice of a udc uses 2 bytes : add + 1 - - - - px11 px10 px9 px8 add (even) px7 px6 px5 px4 px3 px2 px1 px0 px11 is the left most pixel. character slice address : slice address = 64 (character number - 240) + (slice number + 7) x 2. where : - character number is the number given by the character code. - slice number is the number given by the slice interpolator (n of the current slice of the strip : 1 <<18). stv9427 - stv9428 - stv9429 12/20
functional description (continued) hsync r, g, b ld[6:1] = 40 dd[7:0] = 10 nber of characters of the row 16 78081 6.5 active osd video 9427-07.eps figure 7 : hozizontal timing iv - clock and timing the whole timing is derived from the xti and the horizontal synchro input frequencies. the xti input frequency can be an external clock, crystal or a ceramic resonator signal thanks to xti/xto pins. the value of this frequency can be chosen between 6 and 15mhz is used by the pll to generate a pixel clock locked on the horizontal synchro input signal. iv.1 - horizontal timing (see figure 7) the number of pixel periods is given by the line duration register and is equal to : [ld[6:1] x 2 + 1 ] x 12. (ld[6:1] : value of the line duration register). this value allows to define the horizontal size of the characters. the horizontal left margin is given by the hori- zontal delay register and is equal to : (dd[7:0] -6 ) x 6 + 54 (dd[7:0] : value of the display delay register). this value allows to define the horizontal position of the characters on the screen. due to internal logic, minimum horizontal delay is fixed at 4.5 characters (54 pixel) when dd is even and lower or equal to 6, and it is fixed at 5 characters (60 pixel) when dd is odd and lower or equal to 7. iv.2 - d to a timing (stv9427) the d/a converters of the stv9427 are pulse width modulator converter. the frequency of the output signal is : f xtal 256 x 6 and the duty cycle is : vi[7:0] 256 x 6 per cent. after a low pass filter, the average value of the output is : vi [7:0] 256 x 6 v dd v - display control a screen is composed of successive scanlines gath- ered in several strips. each strip is defined by a descriptor stored in memory. a table of descriptors allows screen composition and different tables can be stored in memory at the page addresses (16 possible 1 addresses). two types of strips are available : - spacing strip : its descriptor (see ii) gives the number of black (fbk = 1 in display control register) or transparent (fbk = 0) lines. - character strip : its descriptor gives the memory address of the character codes corresponding to the 1 st displayed character. the characters and attributes (see code format iii) are defined by a succession of codes stored in the ram at ad- dresses starting from the 1 st one given by the descriptor. a character strip can be displayed or not by using the de bit of its descriptor. after the vsync edge, the first strip descriptor is read at the top of the current table of descriptors at the address given by p[9:0] (see display con- trol register) ; if it is a spacing strip, sl[7:0] black or transparent scan lines are displayed ; if it is a character strip, during ch[5:0] scan lines (ch[5:0] given by the character height register), the character codes are read at the addresses starting from the 1 st one given by the descriptor until a end of line character or the end of the scan line ; the next descriptor is then read and the same process is repeated until the next edge of vsync. 1 128 255 v1[7:0] t xtal 256 . t xtal pwm1 signal 0 9427-08.eps figure 8 : pwm timing stv9427 - stv9428 - stv9429 13/20
display control register table of the descriptors 2 nd character strip codes other table of descriptors other (udc for example) 1 st character strip codes 3 rd character srtip codes other (codes or descriptors) spacing row1 row2 spacing row3 spacing ram code and descriptors v-sync top spacing strip 1 st character strip 2 nd character strip 3 rd character strip spacing strip | bottom spacing strip screen osd fbk fl1 p8 p7 p6 p9 fl0 top margin (see note) note : height of top margin is given by top margin register 9427-09.eps figure 9 : relation between screen/address page/character code in ram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 456 36 pixels (= 3 characters) 36 slices (= 2 characters) character number character number on the screen (example for character n5) in the ram slice 1 slice 2 slice 3 slice 4 slice 5 slice 6 slice 7 slice 8 slice 9 slice 10 slice 1 1 slice 12 slice 13 slice 14 slice 15 slice 16 slice 17 slice 18 : 0x00 : 0x08 : 0x0c : 0x0e : 0x0f : 0x0f : 0x0f : 0x0f : 0x0e : 0x0c : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 : 0x00 0xf f 0x7f 0x3f 0x1f 0x1f 0x1f 0x1e 0x1e 0x3c 0x3c 0x78 0x78 0xf1 0x00 0x00 0x00 0x00 0x00 odd address even address msb lsb 9427-10.eps figure 10 : user definable character functional description (continued) stv9427 - stv9428 - stv9429 14/20
9427-11a.eps / 9427-11b.eps table 5 : rom character generator functional description (continued) 234567 0 1 2 3 4 5 6 7 8 9 ab cdef 8 9 a b c d e f stv9427 - stv9428 - stv9429 15/20
filtre %n f xtal vco n . f xtal 9427-12.ai figure 11 : analogic pll algo %m f h-sync %d m . f h-sync err(n) d(n) n . f xtal 9427-13.ai figure 12 : digital pll functional description (continued) vi - pll the pll function of the stv9427/28/29 provides the internal pixel clock locked on the horizontal synchro signal and used by the display processor to generate the r, g, b and fast blancking signals. it is made of 2 plls. the first one analogic (see figure 11), provides a high frequency signal locked on the crystal frequency. the frequency multiplier is given by : n = 2 (fm[3:0] + 3) where fm[3:0] is the value of the frequency multiplier register. the second pll, full digital (see figure 12), pro- vides a pixel frequency locked on the horizontal synchro signal. the ratio between the frequencies of these 2 signals is : m = 12 x (ld[6:1] x 2 + 1) where ld[6:1] is the value of the line duration register. vi.1 - programming of the pll registers frequency multiplier (@3ff8) this register gives the ratio between the crystal frequency and the high frequency of the signal used by the 2 nd pll to provide, by division, the pixel clock. the value of this high frequency must be near to 200mhz (for example if the crystal is a 8mhz, the value of fm must be equal to 10) and greater than 2.5 x (pixel frequency). the frequency of vco must stand within limits given below : f pxlmin x 16 3 f vco 3 f pxlmax x 2.5 initial pixel period (@3ff7) this register allows to increase the speed of the convergence of the pll when the horizontal fre- quency changes (new graphic standart). the rela- tionship between fm[3:0], pp[7:0], ld[6:1], f hsync and f xtal is : pp[7:0] = round ? ? 8 2 ( fm[3:0] + 3 ) f xtal 6 ( ld[6:1] 2 + 1 ) f hsync - 24 ? ? locking condition time constant (@ 3ff5) this register gives the constants as[2:0] and bs[2:0] used by the algo part of the pll (see figure 11) to calculate, from the phase error, err(n), the new value, d(n), of the division of the high frequency signal to provide the pixel clock. these two constants are used only in locking con- dition, which is true, if the phase error is less than a fixed value during at least, 4 scan lines. if the phase error becomes greater than the fixed value, the pll is not in locking condition but in capture process. in this case, the algo part of the pll used the other constants, af[2:0] and bf[2:0], given by the next register. capture process time constant (@ 3ff6) the choice between these two time constants (locking condition or capture process) allows to decrease the capture process time by changing the time response of the pll. stv9427 - stv9428 - stv9429 16/20
functional description (continued) vi.2 - how to choose the value of the time constant ? the time response of the pll is given by its char- acteristic equation which is : ( x - 1 ) 2 + (a + b ) ( x - 1 ) + b = 0. where : a = 3 ld[6:1] 2 a - 11 and b = 3 ld[6:1] 2 b - 19 . (ld[6:1] = value of the line duration register, a = value of the 1st time constant, af or as and b = value of the 2 d time constant, bf or bs). as you can see, the solution depend only on the line duration and the time constants given by the i 2 c registers. if (a + b) 2 - 4 b 3 0 and 2 a - b < 4, the pll is sta- ble and its response is like this presented on figure 13. t pll frequency f 0 f 1 t input frequency f 0 f 1 9427-14.ai figure 13 : time response of the pll/charac- teristic equation solutions (with real solutions) if (a + b) 2 - 4 b 0, the response of the pll is like this presented on figure 14. in this case the pll is stable if t > 0.7 damping coefficient). t pll frequency f 0 f 1 t input frequency f 0 f 1 9427-15.ai figure 14 : time response of the pll/charac- teristic equation solutions (with complex solutions) the table 6 gives some good values for a and b constants for different values of the line dura- tion. summary for a good working of the pll : - a and b time constants must be chosen among values for which the pll is stable, - b must be equal or greater than a and the differ- ence between them must be less than 3, - the greater (a, b) are, the faster the capture is. an optimal choice for the most of applications might be : - for locking condition : as = 0 and bs = 1, - for capture process : af = 2 and bf = 4. but for each application the time constants can be calculated by solving the characteristic equation and choosing the best response. table 6 : valid time constants examples b \ a 0 1 2 3 4 5 6 0 yyyy yyyy yyyy yyyn ynnn nnnn nnnn 1 yyyy yyyy yyyy yyyn ynnn nnnn nnnn 2 nyyy yyyy yyyy yyyn ynnn nnnn nnnn 3 nnny yyyy yyyy yyyn ynnn nnnn nnnn 4 nnnn nyyy (1) yyyy yyyn ynnn nnnn nnnn 5 nnnn nnny yyyy yyyn ynnn nnnn nnnn 6 nnnn nnnn nyyy yyyn ynnn nnnn nnnn 7 nnnn nnnn nnny yyyn ynnn nnnn nnnn 9427-05.tbl note 1 : case of a[2:0] = 1 (001) and b[2:0] = 4 (100) : ld 16 32 48 64 valid time constants nyyy value of line duration register (@ 3ff0) : ld = 16 :ld[6:0] = 0010000, ld[6:1] = 001000 ld = 32 :ld[6:0] = 0100000 ld = 48 :ld[6:0] = 0110000 ld = 64 :ld[6:0] = 1000000, ld[6:1] = 100000. table meaning : n = no possible capture - no stability y = pll can lock stv9427 - stv9428 - stv9429 17/20
pm-dip16.eps package mechanical data (stv9427) 16 pins - plastic dip dimensions millimeters inches min. typ. max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 dip16.tbl stv9427 - stv9428 - stv9429 18/20
pm-dip20.eps package mechanical data (stv9428) 20 pins - plastic dip dimensions millimeters inches min. typ. max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.34 0.053 dip20.tbl stv9427 - stv9428 - stv9429 19/20
pm-dip24.eps package mechanical data (stv9429) 24 pins - plastic dip dimensions millimeters inches min. typ. max. min. typ. max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 d 32.2 1.268 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 27.94 1.100 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 dip24.tbl information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no licence is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or s ystems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved purchase of i 2 c components of stmicroelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. stv9427 - stv9428 - stv9429 20/20

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